In one prior method of and apparatus for asynchronously transferring data between a microprocessor and a memory an acknowledgment signal for the microprocessor is generated by a memory controller. The acknowledgment signal provides the microprocessor with an indication that it is to be responsive to data on a data bus connecting the microprocessor to the memory. In general, the data are coupled to the bus at a time T subsequent to the microprocessor deriving a transfer request signal AS which is coupled to the memory via the controller; the controller responds to the transfer request signal to enable the memory to be addressed by the microprocessor which derived the transfer request signal if all other conditions have been satisfied; e.g. the memory is not performing read or write operations for another microprocessor or a terminal. Such memory controllers are constructed to deliver an acknowledgment signal during a time period t.sub.4 (FIG. 4) which occurs prior to coupling of the data to the bus; for a Motorola 68010 microprocessor having a clock frequency of 10 MHz, the acknowledgment signal must be derived at least 65 nanoseconds before the data is coupled to the bus, if the acknowledgment signal is asynchronous relative to a clock source of the microprocessor.
In order for the acknowledgment signal to be accepted by the microprocessor, the acknowledgment signal must be coupled to the microprocessor at least 20 nanoseconds before the trailing edge of a clock pulse is coupled to the microprocessor. The microprocessor can respond accurately to the data coupled to it by the bus only if the data are coupled to the microprocessor on the data bus at least 15 nanoseconds (t.sub.m, FIG. 4) before the trailing edge of a clock pulse is coupled to the microprocessor. If the microprocessor and memory operate asynchronously, this set of time constraints causes, in most cases, coupling of the data to the microprocessor only after an additional waiting cycle of the microprocessor clock has elapsed, as represented in FIG. 4.